UltraSoC extends on-chip analytics architecture for the age of machine learning, artificial intelligence and parallel computing

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading edge applications such as driverless cars.

Dave Ditzel, Founder and CEO of Esperanto, commented: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

UltraSoC CEO, Rupert Baines, said: “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions – both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety and real-world performance optimization.”

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.